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1 isl34321 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. 16-bit long-reach video serdes with bi-directional side-channel isl34321 the isl34321 is a serializer/deserializer of lvcmos parallel video data. the video data presented to the serializer on the parallel lvcmos bus is serialized into a high-speed differential signal. this differential signal is converted back to parallel video at the remote end by the deserializer. it also transports auxiliary data bidirectionally over the same link during the video vertical retrace interval. i 2 c bus mastering allows the pl acement of external slave devices on the remote side of the link. an i 2 c controller can be place on either side of the link allowing bidirectional i 2 c communication through the link to the external devices on the other side. both chips can be fully configured from a single controller or independently by local controllers. applications* (see page 12) ? video entertainment systems ? industrial computing terminals ? remote cameras features ? 16-bit rgb transport over single differential pair ? 6mhz to 45mhz pixel clock rates ? bi-directional auxiliary data transport without extra bandwidth and over the same differential pair ? hot plugging with automatic resynchronization every hsync. ?i 2 c bus mastering to the remote side of the link with a controller on either the serializer or deserializer ? selectable clock edge for parallel data output ? dc balanced with industry standard 8b/10b line code allows ac-coupling - provides immunity against ground shifts ? 16 programmable settings each for transmitter amplitude boost and pre-emphasis and receiver equalization allow for longer cable lengths and higher data rates ? same device for serializer and deserializer simplifies inventory related literature* (see page 12) ? see isl34341 datasheet fn6827 ?wsvga 24-bit long-reach video serdes with bi-directional side- channel? typical application isl34321 isl34321 rgba/c pclk_in rgba/c ref_clk pclk_in vsync hsync dataen pclk_out vsync hsync dataen video_tx i2ca0 ref_res gnd_cr gnd_p gnd_an gnd_tx gnd_cdr gnd_io video_tx i2ca0 ref_res gnd_cr gnd_p gnd_an gnd_tx gnd_cdr gnd_io seriop serion seriop serion 27nf 27nf 27nf 27nf rstb/pdb vdd_io vdd_cr vdd_p vdd_an vdd_tx vdd_cdr rstb/pdb vdd_io vdd_cr vdd_p vdd_an vdd_tx vdd_cdr 3.16 k 3.16 k 3.3v 1.8v vdd_io 3.3v 1.8v vdd_io vdd_io 10m differential cable 16 16 video source video target vdd_io september 23, 2010 fn6870.1
isl34321 2 fn6870.1 september 23, 2010 block diagram pin configuration isl34321 (48 ld eptqfp) top view 8b/10b x20 rgb v/h/de pclk_in (ref_clk when video_tx is lo) seriop serion sda 16 3 pclk_out x20 tx rx mux demux cdr vcm generator i 2 c scl pre- emphasis eq tdm ram video_tx (hi) 123456789101112 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 vdd_io rgbc0 rgbc1 rgbc2 rgbc3 rgbc4 rgbc5 rgbc6 rgbc7 status rstb/pdb test_en gnd_io vdd_io pclk_op rgba0 rgba1 rgba2 rgba3 rgba4 rgba5 rgba6 rgba7 gnd_io sda scl vdd_p gnd_p pclk_in video_tx vhsyncpol vsync hsync dataen gndcr vddcr vdd_cdr gnd_cdr vdd_tx seriop serion gnd_tx vdd_an gnd_an ref_res master i2ca1 i2ca0 36 35 34 33 32 31 30 29 28 27 26 25
isl34321 3 fn6870.1 september 23, 2010 pin descriptions pin number pin name description serializer deserializer 47, 46 45, 44 43, 42 41, 40 9, 8 7, 6 5, 4 3, 2 rgba7, rgba6 rgba5, rgba4 rgba3, rgba2 rgba1, rgba0 rgbc7, rgbc6 rgbc5, rgbc4 rgbc3, rgbc2 rgbc1, rgbc0 parallel video data lvcmos inputs with hysteresis parallel video data lvcmos outputs 16 hsync horizontal (line) sync lvcmos input with hysteresis horizontal (line) sync lvcmos output 17 vsync vertical (frame) sync lvcmos input with hysteresis vertical (frame) sync lvcmos output 15 dataen video data enable lvcmos input with hysteresis video data enable lvcmos output 20 pclk_in pixel clock lvcmos input p ll reference clock lvcmos input 39 pclk_out default; not used re covered clock lvcmos output 33, 32 seriop, serion high-speed differential serial i/o high sp eed differential serial i/o 18 vhsyncpol cmos input for hsync and vsync polarity 1: hsync & vsync active low 0: hsync & vsync active high 19 video_tx cmos input for video flow direction 1: video serializer 0: video deserializer 24, 23 sda, scl (note 1) i 2 c interface pins (i 2 c data, i 2 c clk) 25, 26 i2ca[1:0] (note 1) i 2 c device address 27 master i 2 c master mode 1: master 0: slave 12 rstb/pdb cmos input for reset and power-down. fo r normal operation, this pin must be forced high. when this pin is forced lo w, the device will be reset. if this pin stays low, the device will be in pd mode. 10 status cmos output for receiver status: 1: valid 8b/10b data received 0: otherwise note: serializer and deserializer switch roles during side-cha nnel reverse traffic 28 ref_res analog bias setting resistor connection; use 3.16k 1% to ground 21 gnd_p (note 2) pll ground 37, 48 gnd_io (note 2) digital (parallel and control) ground 35 gnd_cdr (note 2) analog (serial) data recovery ground 31 gnd_tx (note 2) analog (serial) output ground 29 gnd_an (note 2) analog bias ground 13 gnd_cr (note 2) core logic ground 14 vdd_cr core logic vdd 34 vdd_tx analog (serial) output vdd 30 vdd_an analog bias vdd
isl34321 4 fn6870.1 september 23, 2010 36 vdd_cdr analog (serial) data recovery vdd 1, 38 vdd_io (note 1) digital (parallel and control) vdd 22 vdd_p pll vdd 11 test_en must be connected to ground exposed pad pd must be connected to ground notes: 1. pins with the same name are internally connected together . however, this connection must not be used for connecting together external comp onents or features. 2. the various differently-named ground pins are internally weakly connected. they must be tied together externally. the different names are provided to assist in minimizing the curr ent loops involved in bypassing the associated supply vdd pins. in particular, for esd test ing, they should be considered a common connection pin descriptions (continued) pin number pin name description serializer deserializer ordering information part number (notes 3, 4, 5) part marking temp. range (c) package (pb-free) pkg. dwg. # isl34321inz isl34321 inz -40 to +85 48 ld eptqfp q48.7x7b 3. add ?-t13? suffix for tape and reel. please refer to tb347 for details on reel specifications. 4. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matt e tin plate plus anneal (e3 termin ation finish, which is rohs comp liant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl34321 . for more information on msl please see techbrief tb363 .
isl34321 5 fn6870.1 september 23, 2010 absolute maximum ratings thermal information supply voltage vdd_p to gnd_p, vdd_tx to gnd_tx, vdd_io to gnd_io . . . . . . . . . . . . . . . . -0.5v to 4.6v vdd_cdr to gnd_cdr, vdd_cr to gnd_cr -0.5v to 2.5v between any pair of gnd_p, gnd_tx, gnd_io, gnd_cdr, gnd_cr . . . . . . . . . . -0.1v to 0.1v 3.3v tolerant lvttl/lvcmos input voltage . . . . . . . . . . . . . . . .-0.3v to vdd_io+0.3v differential input voltage . . . . . . . .-0.3v to vdd_io + 0.3v differential output current . . . . . . . . short circuit protected lvttl/lvcmos outputs . . . . . . . . . . short circuit protected esd rating human body model all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kv seriop/n (all vdd connected , all gnd connected) . 8kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v latch up (tested per jesd-78b ; class2, level a). . . .100ma thermal resistance (typical) ja jc (c/w) eptqfp (notes 6, 7) . . . . . . . . . . . 38 12 maximum power dissipation . . . . . . . . . . . . . . . . . . . . 327mw maximum junction temperature . . . . . . . . . . . . . . +125c maximum storage temperature range . . . -65c to +150c operating temperature range . . . . . . . . . . -40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. parameter symbol conditions min typ max units power supply voltage vdd_cdr, vdd_cr 1.7 1.8 1.9 v vdd_tx, vdd_p, vdd_an, vdd_io 3.0 3.3 3.6 v serializer power supply currents total 1.8v supply current pclk_in = 45mhz 62 80 ma total 3.3v supply current (note 8) 40 52 ma deserializer power supply currents total 1.8v supply current pclk_in = 45mhz 66 76 ma total 3.3v supply current (note 8) 50 63 ma power-down supply current total 1.8v power-down supply current rstb = gnd 10 ma total 3.3v power-down supply current 0.5 ma parallel interface high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input leakage current i in -1 0.01 1 a high level output voltage v oh i oh = -4.0ma, vdd_io = 3.0v 2.6 v low level output voltage v ol i ol = 4.0ma, vdd_io = 3.6v 0.4 v output short circuit current i osc 35 ma
isl34321 6 fn6870.1 september 23, 2010 output rise and fall times t or /t of slew rate control set to min c l = 8pf 1ns slew rate control set to max, c l = 8pf 4ns serializer parallel interface pclk_in frequency f in 645mhz pclk_in duty cycle t idc 40 50 60 % parallel input setup time t is 3.5 ns parallel input hold time t ih 1.0 ns deserializer parallel interface pclk_out frequency f out 645mhz pclk_out duty cycle t odc 50 % pclk_out period jitter (rms) t oj clock randomizer off 0.5 %t pclk pclk_out spread width t osprd clock randomizer on 20 %t pclk pclk_out to parallel data outputs (includes sync and de pins) t dv relative to pclk_out, (note 9) -1.0 5.5 ns deserializer output latency t cpd inherent in the design 4 9 14 pclk deserializer reference clock (ref_clk is fed into pclk_in) ref_clk lock time t pll 100 s ref_clk to pclk_out maximum frequency offset pclk_out is the recovered clock 1500 5000 ppm high-speed transmitter hs differential output voltage, tra nsi ti on bi t vod tr txcn = 0x00 650 800 900 mv p-p txcn = 0x0f 900 mv p-p txcn = 0xf0 1100 mv p-p txcn = 0xff 1300 mv p-p hs differential output voltage, non- tra nsi ti on bi t vod ntr txcn = 0x00 650 800 900 mv p-p txcn = 0x0f 900 mv p-p txcn = 0xf0 430 mv p-p txcn = 0xff 600 mv p-p hs generated output common mode voltage v ocm 2.35 v hs common mode serializer- deserializer voltage difference v cm 10 20 mv hs differential output impedance r out 80 100 120 hs output latency t lpd inherent in the design 4 7 10 pclk hs output rise and fall times t r/ t f 20% to 80% 150 ps hs differential skew t skew <10 ps hs output random jitter t rj pclk_in = 45mhz 6 ps rms hs output deterministic jitter t dj pclk_in = 45mhz 25 ps p-p electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. (continued) parameter symbol conditions min typ max units
isl34321 7 fn6870.1 september 23, 2010 high speed receiver hs differential input voltage v id 75 mv p-p hs generated input common mode voltage v icm 2.32 v hs differential input impedance r in 80 100 120 hs maximum jitter tolerance 0.50 ui p-p i 2 c i 2 c clock rate (on scl) f i2c 100 400 khz i 2 c clock pulse width (hi or lo) 1.3 s i 2 c clock low to data out valid 0 1 s i 2 c start/stop setup/hold time 0.6 s i 2 c data in setup time 100 ns i 2 c data in hold time 100 ns i 2 c data out hold time 100 ms notes: 8. iddio is nominally 50a and not included in this total as it is dominated by the loading of the parallel pins 9. this parameter is the output data skew from the invalid edge of pclk_out. the setup and hold time provided to a system is dependent on the pclk frequency and is calculated as follows: 0.5 * f in - t dv. . electrical specifications unless otherwise indicated, all data is for: vdd_cdr = vdd_cr = 1.8v, vdd_io = 3.3v , vdd_tx = vdd_p = vdd_an = 3.3v, t a = +25c, ref_res = 3.16k , high-speed ac-coupling capacitor = 27nf. (continued) parameter symbol conditions min typ max units
isl34321 8 fn6870.1 september 23, 2010 diagrams 0x00 0x0f 0xf0 0xff vod tr txcn vod ntr figure 1. vod vs. txcn setting figure 2. parallel video input timing [pclk_in active low, hsync/vsync active high] hsync vsync dataen pclk_in rgb[a:c][7:0] 1/f in t idc t is t ih t is t ih valid data valid data data ignored data ignored valid data video_tx = 1
isl34321 9 fn6870.1 september 23, 2010 applications detailed description and operation a pair of isl34321 serdes transports 16-bit parallel video for the isl34321 along with auxiliary data over a single 100 differential cable either to a display or from a camera. auxiliary data is transferred in both directions and can be used for remote configuration and telemetry. the benefits include lower emi, lower costs, greater reliability and space savings. the same device can be configured to be either a serializer or deserializer by setting one pin (video_tx), simplifying inventory. rgba/b/c, vsync, hsync, and dataen pins are inputs in serializer mode and outputs in deserializer mode. the video data presented to th e serializer on the parallel lvcmos bus is serialized into a high-speed differential signal. this differential signal is converted back to parallel video at the remote end by the deserializer. the side channel data is tran sferred between the serdes pair during two lines of the vertical video blanking interval. when the side-channel is enab led, there will be a number of pclk cycles uncertainty from frame-to-frame. this should not cause sync problems with most displays, as this occurs during the vertical front porch of the blanking period. when properly co nfigured, the serdes link supports end-to-end transport with fewer than one error in 10 10 bits. differential signals and termination the isl34321 serializes the 16-bit parallel data plus 3 sync signals at 20x the pclk_in frequency. the extra 2 bits per word come from the 8b/10b encoding scheme which helps create the highest quality serial link. the high bit rate of the differential serial data requires special care in the layout of traces on pcbs, in the choice and assembly of connectors, and in the cables themselves. pcb traces need to be adjacent and matched in length (so as to minimize the imbalanced coupling to other traces or elements) and of a geometry to match the impedance of the transmitter and receiver to minimize reflections. similar care needs to be applied to the choice of connectors and cables. seriop and serion pins incorporate internal differential termination of the serial signal lines. serio pin ac-coupling ac-coupling minimizes the effects of dc common mode voltage difference and local power supply variations between two serdes. the serializer outputs dc balanced 8b/10b line code, which allows ac-coupling. the ac-coupling capacitor on serio pins must be 27nf on the serializer board and 27nf on the deserializer board. the value of the ac-coupling capacitor is very critical since a value too small will attenuate the high speed signal at low clock rate. a value too big will slow down the turn around time for the side-channel. it is an advantage to have the pair of capacitors as closely matched as possible. receiver reference clock (ref_clk) the reference clock (ref_clk) for the pll is fed into pclk_in pin. ref_clk is used to recover the clock from the high speed serial stream. ref_clk is very sensitive to any instability. the following conditions must be met at all times after power is applied to the deserializer, or else the deserializer may need a manual reset: ? vdd must be applied and stable. ? ref_clk frequency must be within the limits specified ? ref_clk amplitude must be stable. a simple 3.3v cmos crystal oscillator can be used for ref_clk. figure 3. parallel video output timing [p clk_out active low, hsync/vsync active high] hsync vsync dataen pclk_out rgb[a:c][7:0] 1/f out t odc t or t dv t of valid data valid data data held at previous value valid data t dv video_tx = 0
isl34321 10 fn6870.1 september 23, 2010 power supply sequencing the 3.3v supply must be higher than the 1.8v supply at all times, including during power-up and power-down. to meet this requirement, the 3.3v supply must be powered up before the 1.8v supply. for the deserializer, ref_clk must not be applied before the device is fully powered up. applying ref_clk before power-up may require the deserializer to be manually reset. a 10ms delay after the 1.8v supply is powered up guarantees normal operation. power supply bypassing and layout the serializer and deserializer functions rely on the stable functioning of plls locked to local reference sources or locked to an incoming signal. it is important that the various supplies (vdd_p, vdd_an, vdd_cdr, vdd_tx) be well bypassed over a wide range of frequencies, from below the typical loop bandwidth of the pll to approaching the signal bit rate of the serial data. a combination of different values of capacitors from 1000pf to 5f or more with low esr characteristics is generally required. the parallel lvcmos vdd_io supply is inherently less sensitive, but since the rgb and sync/dataen signals can all swing on the same clock edge, the current in these pins and the corresponding gnd pins can undergo substantial current flow changes, so once again, a combination of different values of capacitors over a wide range, with low esr characteristics, is desirable. a set of arrangements of this type is shown in figure 4, where each supply is bypassed with a ferrite-bead-based choke, and a range of capacitors. a ?choke? is preferable to an ?inductor? in this application, since a high-q inductor will be likely to cause one or more resonances with the shunt capacitors, potentially causing problems at or near those frequencies, while a ?lossy? choke will reflect a high impedance over a wide frequency range. the higher value capacitor, in particular, needs to be chosen carefully, with special care regarding its esr. very good results can be obtained with multilayer ceramic capacitors, available from many suppliers, and generally in small outlines (such as the 1210 outline suggested in the schematic shown in figure 4), which provide good bypass capabilities down to a few m at 1mhz to 2mhz. other capacitor technologies may also be suitable (perhaps niobium oxide), but ?classic? electrolytic capacitors frequently have esr values of above 1 , that nullify any decoupling effect above the 1khz to 10khz frequency range. capacitors of 0.1f offer low impedance in the 10mhz to 20mhz region, and 1000pf capacitors in the 100mhz to 200mhz region. in general, one of the lower value capacitors should be used at each supply pin on the ic. figure 4 shows the grounding of the various capacitors to the pin corresponding to the supply pin. although all the ground supplies are tied together, the pcb layout should be arranged to emulate this arrangement, at least for the smaller value (high frequency) capacitors, as much as possible. i 2 c interface the i 2 c interface allows access to internal registers used to configure the serdes and to obtain status information. a serializer must be assigned a different address than its deserializer counterpart. the upper 5 bits are permanently set to 011 11 and the lower 2bits determined by pins as follows: thus, 16 serdes can reside on the same bus. by convention, when all address pins are tied low, the device address is referred to as 0x78. scl and sda are open drain to allow multiple devices to share the bus. if not used, sc l and sda should be tied to vdd_io. side channel interface the side channel is a mechanism for transferring data between the two chips on each end of the link. this data is transferred during video blanking so none of the video bandwidth is used. it has three basic uses: ? data exchanges between two processors ?master mode i 2 c commands to remote slaves ? remote serdes configuration this interface allows the user to initialize registers, control and monitor both se rdes chips from a single micro controller which can reside on either side of the serial link. this feature is used to automatically transport the remote side serdes chip?s status back to a local register. the side channel needs to be enabled (the default) for this to work. in the case where there is a micro controller on each side of the of the link, data can be buffered and exchanged between the two. up to 224 bytes can be sent in each direction during each vsync active period. 01111i2ca1i2ca0r/w figure 4. power supply bypassing
isl34321 11 fn6870.1 september 23, 2010 master mode this is a mode activated by strapping the master pin to a ?1? on the isl34321 on the remote side of the controller. this is a virtual extension of the i 2 c interface across the link that allows the local processor to read and write slave devices connected to the remote side serdes i 2 c bus. no additional wires or components are needed other than the serial link. the i 2 c commands and data are transferred during video blanking causing no interruptions in the video data. in master mode the data is transported across the link by the side channel so the maximum throughput achievable would be the same. the scl and sda frequency is adjustable through the programming of a register. exposed pad while it is not a required electrical connection, it is recommended that the expose d pad on the bottom of the package be soldered to the ci rcuit board. this will ensure that the full power dissipation of the package can be utilized. the pad should be connected to ground and not left floating. for best thermal conductivity 9 - 25 vias should connect the footprint for the exposed pad on the circuit board to the ground plane. copper pad vias 25x figure 5. layout fo r the exposed pad
isl34321 12 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6870.1 september 23, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl34321 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 7/15/10 fn6870.1 updated ?package outline drawing? on page 13. changes were: updated the format by moving dimensions from table onto drawing and adding land pattern. 5/14/10 converted to new intersil template updated ordering information by adding msl note removed from features section: ? internal 100 termination on high -speed serial lines ? programmable powerdown of th e transmitter and the receiver ? i2c communication interface ? 8kv esd rating for serial lines ? pb-free (rohs compliant) changed order of follow ing items in datasheet: -moved block diagram to immediately fo llow page 1 then pin configuration -pin description table moved to immediately follow pinout -ordering information to follow pin descriptions added latch-up to abs max ratings added diagrams and applicatio ns section, revision histor y and products information 3/16/09 fn6870.0 initial release to web
isl34321 13 fn6870.1 september 23, 2010 package outline drawing q48.7x7b 48 lead thin plastic quad flatpack exposed pad package rev 2, 7/10 bottom view detail "a" typical recommended land pattern top view 0.20 min. (1.00) 0.09/0.20 0.17/0.23 base metal 0.09/0.16 7 0.17/0.27 11/13 with lead finish 0.08 c ma-b d 0.05/0.15 see detail "a" c 0.08 1.20 max 1.00 0.05 h gauge 0.60 0.15 0-7 0.25 0 min. 0.50 3 a 5 4 d 3 9.00.20 4 5 exposed pad 4.000.1 2 (10.00) (4.00) (0.28) typ (4.00) (1.50) typ 4.000.1 (10.00) 3 b 9.00.20 7.00.10 7.00.10 plane notes: ms-026, variation abc-hd. 8. controlling dimension: millimeter. this outline conforms to jedec publication 95 registration condition. dambar cannot be located on the lower radius or dambar protrusion shall be 0.08mm total at maximum material dimension does not include dambar protrusion. allowable 6. package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package. 1. all dimensioning and tolerancing conform to ansi y14.5-1982. 2. datum plane h located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. datums a-b and d to be determined at centerline between leads where leads exit plastic body at datum plane h. 4. dimensions do not include mold protrusion. allowable mold protrusion is 0.254mm on d1 and e1 dimensions. 9. 7. 5. these dimensions to be determined at datum plane h. 10. dimensions in ( ) are for reference only. the foot.

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